1. Field of the Invention
Example embodiments relate to a memory system for controlling power, and method thereof. More particular, example embodiments may relate to a memory system and a method of adaptive power throttling according to a power characteristic of a memory device.
2. Description of the Related Art
Recently, as data transmission speed of a processor increases over a short period of time, e.g., several GHz, a memory device having mass storage and high speed may be required. In addition, power consumption may increase as the speed of the memory device increases. Therefore, the power consumption of the memory device may have to be considered when designing the memory system. Further, other power consumption factors, such as, a battery life of portable applications, a cooling device of desk tops, and a power design of a server field, may have to be considered when designing the memory system.
The power consumption of a double data rate synchronous dynamic random access memory (DDR SDRAM) may generally be lower than that of other memory devices. A data manual for the DDR SDRAM may provide operation currents according to each command. For instance, in the DDR SDRAM, when a successive bank access operation is performed according to a multi-bank access method, a high active operation current may flow in a continuous manner. Accordingly, joint electron device engineering council (JEDEC) standards may specify that the bank access operation may not be successively performed more than four times.
A conventional memory controller may generate a power weight value based on a command type. A power count of memory ranks may be increased based on the power weight value generated from the memory controller, and then the power count of the memory ranks may be compared with a threshold value that may be set for the memory ranks. The memory controller may throttle the power of the memory ranks, such that the power count may not exceed the threshold value, e.g., the power consumption may be decentralized by controlling generation time of the command that may be generated from the memory controller.
However, in the conventional power throttling scheme, a power characteristic of the memory device may not reflect the power throttling because the power consumption may be controlled by counting the power weight value of the command, which may be applied to the memory ranks from the memory controller.
Further, because the power characteristic of the memory device may be determined by a system designer by consulting the power characteristic of the memory device, which may be obtain through manual written data, the design may be tedious, troublesome and complicated.